System on chip designs are becoming common where a single chip houses a plurality of logically separate functional blocks. Examples of functional blocks include a clock control block, security block, Analogue to Digital converter and other functional blocks applicable to the system.
Often the clock control block will include functionality for generating a variety of clock signals of different frequencies that may be used by the other functional blocks on chip. These frequencies may be generated with a circuit such as a software programmable phase locked loop (PLL) clock divider.
Functional blocks that receive clock signals from the PLL clock divider have no direct control over the frequency of those clock signals and the functional block accepts that the frequency provided to it is correct and has not been tampered with.
Situations may arise where the frequency of a clock signal received by a functional block cannot be trusted. For example, if an extremely low frequency clock signal is provided the operation of a functional block may be impaired. For example, a security block designed to be clocked by a specific clock frequency should maintain its correct frequency to keep the integrity of its function.
The change in clock frequency may come about purposively, for example a PLL clock divider may be erroneously programmed by software to output a frequency much lower than the ideal operating clock frequency of the functional block. Alternatively the clock control functional block may malfunction. In either case the operation of the security block may be impaired.